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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998 data sheet mos integrated circuit MC-458DA726 8 m-word by 72-bit synchronous dynamic ram module registered type document no. m13202ej3v0ds00 (3rd edition) date published march 1999 ns cp(k) printed in japan the mark h h h h shows major revised points. description the MC-458DA726 is a 8,388,608 words by 72 bits synchronous dynamic ram module on which 9 pieces of 64m sdram: m pd4564841 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features 8,388,608 words by 72 bits organization (ecc type) clock frequency and access time from clk part number /cas latency clock frequency access time from clk (max.) (max.) MC-458DA726f-a80 cl = 3 125 mhz 6 ns cl = 2 100 mhz 6 ns MC-458DA726f-a10 cl = 3 100 mhz 6 ns cl = 2 77 mhz 7 ns MC-458DA726lf-a80 cl = 3 125 mhz 6 ns cl = 2 100 mhz 6 ns MC-458DA726lf-a10 cl = 3 100 mhz 6 ns cl = 2 77 mhz 7 ns fully synchronous dynamic ram, with all signals referenced to a positive clock edge pulsed interface possible to assert random column address in every cycle quad internal banks controlled by ba0 and ba1 (bank select) programmable burst-length (1, 2, 4, 8 and full page) programmable wrap sequence (sequential / interleave) programmable /cas latency (2, 3) automatic precharge and controlled precharge cbr (auto) refresh and self refresh all dqs have 10 w 10 % of series resistor single 3.3 v 0.3 v power supply lvttl compatible 4,096 refresh cycles/64 ms burst termination by burst stop command and precharge command 168-pin dual in-line memory module (pin pitch = 1.27 mm) registered type serial pd pc100 registered dimm rev. 1.0 compliant h h h
data sheet m13202ej3v0ds00 2 MC-458DA726 ordering information part number clock frequency mhz (max.) package mounted devices MC-458DA726f-a80 125 mhz 168-pin dual in-line memory module 9 pieces of m pd4564841g5 (rev. e) MC-458DA726f-a10 100 mhz (socket type) (400 mil tsop (ii)) MC-458DA726lf-a80 125 mhz edge connector: gold plated 9 pieces of m pd4564841g5 (rev. l) MC-458DA726lf-a10 100 mhz 38.1 mm (1.5 inch) height (400 mil tsop (ii)) h h
data sheet m13202ej3v0ds00 3 MC-458DA726 pin configuration 168-pin dual in-line memory module socket type (edge connector : gold plated) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 v ss dq32 dq33 dq34 dq35 vcc dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 vcc cb5 v ss nc nc vcc /cas dqmb4 dqmb5 nc /ras v ss a1 a3 a5 a7 a9 ba0 (a13) a11 vcc clk1 nc v ss cke0 nc dqmb6 dqmb7 nc vcc nc nc cb6 cb7 v ss dq48 dq49 dq50 dq51 vcc dq52 nc nc rege v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 vcc dq60 dq61 dq62 dq63 v ss clk3 nc sa0 sa1 sa2 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 v ss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 cb0 cb1 v ss nc nc vcc /we dqmb0 dqmb1 /cs0 nc v ss a0 a2 a4 a6 a8 a10 ba1(a12) vcc vcc clk0 v ss nc /cs2 dqmb2 dqmb3 nc vcc nc nc cb2 cb3 v ss dq16 dq17 dq18 dq19 vcc dq20 nc nc nc v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 vcc dq28 dq29 dq30 dq31 v ss clk2 nc wp sda scl vcc dq46 dq47 cb4 /xxx indicates active low si gnal. a0 - a11 : address inputs [row: a0 - a11, column: a0 - a8] ba0 (a13), ba1 (a12) : sdram bank select dq0 - dq63, cb0 - cb7 : data inputs/outputs clk0 - clk3 : clock input cke0 : clock enable input wp : write protect note /cs0, /cs2 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqmb0 - dqmb7 : dq mask enable sa0 - sa2 : address input for eeprom sda : serial data i/o for pd scl : clock input for pd v cc : power supply v ss : ground rege : register / buffer enable nc : no connection note wp is not used yet. it is connected to ground.
data sheet m13202ej3v0ds00 4 MC-458DA726 block diagram rdqmb0 /rcs0 rdqmb2 dqm d0 /cs dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 d1 dqm /cs dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 d2 dqm /cs dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 dq 2 dq 0 dq 7 dq 5 dq 3 dq 1 dq 6 dq 4 d3 dqm /cs dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 d4 dqm /cs d7 dqm /cs dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 d8 dqm /cs d6 dqm /cs dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dqm d5 /cs dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 cb 0 cb 1 cb 2 cb 3 cb 4 cb 5 cb 6 cb 7 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 rdqmb1 rdqmb4 rdqmb5 rdqmb7 rdqmb6 rdqmb3 serial pd sda a0 a1 a2 sa0 sa1 sa2 v cc d0 - d8, register1, register2, pll d0 - d8, register1, register2, pll gnd c /cs0 dqmb0, 1, 4, 5 /ras /cas /we a0 - a7 /rras /rcas /rwe /cs2 dqmb2, 3, 6, 7 cke0 a8 - a11, ba0, ba1 rege /le /le rcke0 ra10, ra11, rba0, rba1 clk1 clk2 clk3 30 pf 10 w dq 0 10 w 10 w 10 w 10 w 10 w 10 w 10 w 10 w 10 w register1 register2 /rcs2 30 pf 15 pf 30 pf 30 pf 30 pf 30 pf 30 pf 30 pf 15 pf dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 10 k w v cc scl clk0 10 pf 20 w clk : d2,d3,d6 clk : d4,d7,d8 clk : register 1, register 2 pll clk : d0,d1,d5 ra0 - ra7 /ras : d0 - d8 /cas : d0 - d8 /we : d0 - d8 a0 - a7 : d0 - d8 cke : d0 - d8 a10, a11, ba0, ba1 : d0 - d8 /rcs2 rdqmb2, 3, 6, 7 15 pf /rcs0 rdqmb0, 1, 4, 5 15 pf wp 47 k w remarks 1. the series register values of dqs are 10 w . 2. wp is not used yet. it is connected to ground. 3. d0 - d8: m pd4564841 (2m words 8 bits 4 banks) 4. rege v il : buffer mode rege 3 v ih : register mode 5. register: sn74alvc162334dgg pll: cdc2509apw
data sheet m13202ej3v0ds00 5 MC-458DA726 electrical specifications all voltages are referenced to v ss (gnd). after power up, wait more than 1 ms and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 11 w operating ambient temperature t a 0 to +70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 + 0.8 v operating ambient temperature t a 070 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11, ba0(a13), ba1(a12), /ras, /cas, /we 410pf c i2 clk0 - clk3 15 35 c i3 cke0 4 10 c i4 /cs0, /cs2 4 10 c i5 dqmb0 -dqmb7 4 10 data input/output capacitance c i/o dq0 - dq63, cb0 - cb7 6 13 pf
data sheet m13202ej3v0ds00 6 MC-458DA726 dc characteristics (recommended operating conditions unless otherwise noted) [MC-458DA726f] parameter symbol test condition min. max. unit notes operating current i cc1 burst length = 1, t rc 3 t rc(min.) , /cas latency = 2 -a80 1,020 ma 1 i o = 0 ma -a10 930 /cas latency = 3 -a80 1,065 -a10 975 precharge standby current in i cc2 p cke v il(max.) , t ck = 15 ns 259 ma power down mode i cc2 ps cke v il(max.) , t ck = 14.5 precharge standby current in non power down mode i cc2 ncke 3 v ih (min.) , t ck = 15 ns, /cs 3 v ih (min.) , input signals are changed one time during 30 ns. 430 ma i cc2 ns cke 3 v ih (min.) , t ck = , input signals are stable. 54 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 295 ma power down mode i cc3 ps cke v il(max.) , t ck = 36 active standby current in i cc3 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , 475 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke 3 v ih (min.) , t ck = , input signals are stable. 90 operating current i cc4 t ck 3 t ck(min.) , i o = 0 ma /cas latency = 2 -a80 1,245 ma 2 (burst mode) -a10 1,020 /cas latency = 3 -a80 1,425 -a10 1,245 cbr (auto) refresh current i cc5 t rc 3 t rc(min.) /cas latency = 2 -a80 1,470 ma 3 -a10 1,470 /cas latency = 3 -a80 1,515 -a10 1,515 self refresh current i cc6 cke 0.2 v 259 ma input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C 10 + 10 m a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 vC 1.5 + 1.5 m a high level output voltage v oh i o = C 4.0 ma 2.4 v low level output voltage v ol i o = + 4. 0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck (min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) .
data sheet m13202ej3v0ds00 7 MC-458DA726 [MC-458DA726lf] parameter symbol test condition min. max. unit notes operating current i cc1 burst length = 1, t rc 3 t rc(min.) , /cas latency = 2 -a80 1,020 ma 1 i o = 0 ma -a10 930 /cas latency = 3 -a80 1,065 -a10 975 precharge standby current in i cc2 p cke v il(max.) , t ck = 15 ns 259 ma power down mode i cc2 ps cke v il(max.) , t ck = 21 precharge standby current in non power down mode i cc2 ncke 3 v ih (min.) , t ck = 15 ns, /cs 3 v ih (min.) , input signals are changed one time during 30 ns. 430 ma i cc2 ns cke 3 v ih (min.) , t ck = , input signals are stable. 54 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 295 ma power down mode i cc3 ps cke v il(max.) , t ck = 36 active standby current in i cc3 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , 475 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke 3 v ih (min.) , t ck = , input signals are stable. 135 operating current i cc4 t ck 3 t ck(min.) , i o = 0 ma /cas latency = 2 -a80 1,245 ma 2 (burst mode) -a10 1,020 /cas latency = 3 -a80 1,425 -a10 1,245 cbr (auto) refresh current i cc5 t rc 3 t rc(min.) /cas latency = 2 -a80 1,470 ma 3 -a10 1,470 /cas latency = 3 -a80 1,515 -a10 1,515 self refresh current i cc6 cke 0.2 v 259 ma input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C 10 + 10 m a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 vC 1.5 + 1.5 m a high level output voltage v oh i o = C 4.0 ma 2.4 v low level output voltage v ol i o = + 4. 0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck (min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) . h
data sheet m13202ej3v0ds00 8 MC-458DA726 ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions ac measurements assume t t = 1 ns. reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max.) . an access time is measured at 1.4 v. t ck t ch t cl 2.0 v 1.4 v 0.8 v clk 2.0 v 1.4 v 0.8 v input t setup t hold output t ac t oh
data sheet m13202ej3v0ds00 9 MC-458DA726 synchronous characteristics (registered mode) parameter symbol -a80 -a10 unit note min. max. min. max. clock cycle time /cas latency = 3 t ck3 8 (125 mhz) 10 (100 mhz) ns /cas latency = 2 t ck2 10 (100 mhz) 13 (77 mhz) ns access time from clk /cas latency = 3 t ac3 66ns1 /cas latency = 2 t ac2 67ns1 input clk duty cycle 40 60 40 60 % data-out hold time /cas latency = 3 t oh3 33ns1 /cas latency = 2 t oh2 33ns1 data-out low-impedance time t lz 00ns data-out high- /cas latency = 3 t hz3 3636ns impedance time /cas latency = 2 t hz2 3637ns data-in setup time t ds 22ns data-in hold time t dh 11ns address setup time t as 1.5 1.5 ns address hold time t ah 0.9 0.9 ns cke setup time t cks 1.5 1.5 ns cke hold time t ckh 0.9 0.9 ns cke setup time (power down exit) t cksp 1.5 1.5 ns command (/cs0 - /cs3, /ras, /cas, /we, dqmb0 - dqmb7) setup time t cms 1.5 1.5 ns command (/cs0 - /cs3, /ras, /cas, /we, dqmb0 - dqmb7) hold time t cmh 0.9 0.9 ns note 1. output load output z = 50 w 1.4 v 50 pf 50 w remark these specifications are applied to the monolithic device.
data sheet m13202ej3v0ds00 10 MC-458DA726 asynchronous characteristics (registered mode) parameter symbol -a 80 -a10 unit note min. max. min. max. ref to ref/act command period t rc 70 70 ns act to pre command period t ras 48 120,000 50 120,000 ns pre to act command period t rp 20 20 ns delay time act to read/write command t rcd 20 20 ns act(0) to act(1) command period t rrd 16 20 ns data-in to pre command period t dpl - 1clk+8 - 1clk+10 ns data-in to act(ref) command period /cas latency = 3 t dal3 20 20 ns (auto precharge) /cas latency = 2 t dal2 20 20 ns mode register set cycle time t rsc 22clk transition time t t 0.530130ns refresh time (4,096 refresh cycles) t ref 64 64 ms
data sheet m13202ej3v0ds00 11 MC-458DA726 serial pd (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written into serial pd memory 80h 1 0 0 0 0 0 0 0 128 bytes 1 total number of bytes of serial pd memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 04h 0 0 0 0 0 1 0 0 sdram 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 09h 0 0 0 0 1 0 0 1 9 columns 5 number of banks 01h 0 0 0 0 0 0 0 1 1 bank 6 data width 48h 0 1 0 0 1 0 0 0 72 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 cl = 3 cycle time -a80 80h 1 0 0 0 0 0 0 0 8 ns -a10 a0h 1 0 1 0 0 0 0 0 10 ns 10 cl = 3 access time -a80 60h 0 1 1 0 0 0 0 0 6 ns -a10 60h 0 1 1 0 0 0 0 0 6 ns 11 dimm configuration type 02h 0 0 0 0 0 0 1 0 ecc 12 refresh rate/type 80h 1 0 0 0 0 0 0 0 normal 13sdram width 08h00001000 8 14 error checking sdram width 08h 0 0 0 0 1 0 0 0 8 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 8fh 1 0 0 0 1 1 1 1 1, 2, 4, 8, f 17 number of banks on each sdram 04h 0 0 0 0 0 1 0 0 4 banks 18 /cas latency supported 06h 0 0 0 0 0 1 1 0 2, 3 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 01h 0 0 0 0 0 0 0 1 0 21 sdram module attributes 1fh 0 0 0 1 1 1 1 1 registered 22 sdram device attributes : general 0eh 0 0 0 0 1 1 1 0 23 cl = 2 cycle time -a80 a0h 1 0 1 0 0 0 0 0 10 ns -a10 d0h 1 1 0 1 0 0 0 0 13 ns 24 cl = 2 access time -a80 60h 0 1 1 0 0 0 0 0 6 ns -a10 70h 0 1 1 1 0 0 0 0 7 ns 25-26 00h 0 0 0 0 0 0 0 0 27 t rp(min.) -a80 14h 0 0 0 1 0 1 0 0 20 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns 28 t rrd(min.) -a80 10h 0 0 0 1 0 0 0 0 16 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns 29 t rcd(min.) -a80 14h 0 0 0 1 0 1 0 0 20 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns 30 t ras(min.) -a80 30h 0 0 1 1 0 0 0 0 48 ns -a10 32h 0 0 1 1 0 0 1 0 50 ns 31 module bank density 10h 0 0 0 1 0 0 0 0 64m bytes
data sheet m13202ej3v0ds00 12 MC-458DA726 (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 32 command and address signal input setup time 15h 0 0 0 1 0 1 0 1 1.5 ns 33 command and address signal input hold time 09h 0 0 0 0 1 0 0 1 0.9 ns 34 data signal input setup time 20h 0 0 1 0 0 0 0 0 2 ns 35 data signal input hold time 10h 0 0 0 1 0 0 0 0 1 ns 36-61 00h 0 0 0 0 0 0 0 0 62 spd revision 12h 0 0 0 1 0 0 1 0 1.2 63 checksum for bytes 0 - 62 -a80 feh 1 1 1 1 1 1 1 0 -a10 64h01100100 64-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91 revision code 93-94 manufacturing date 95-98 assembly serial number 99-125 mfg specific 126 intel specification frequency 64h 0 1 1 0 0 1 0 0 100 mhz 127 intel specification /cas -a80 87h 1 0 0 0 0 1 1 1 latency support -a10 85h 1 0 0 0 0 1 0 1 timing chart refer to the synchronous dram module timing chart information (m13348x) . h
data sheet m13202ej3v0ds00 13 MC-458DA726 package drawing 168 pin dual in-line module (socket type) n m t u p d item millimeters u 4.0 min. s t 1.270.1 a b 11.43 133.350.13 c d 6.35 36.83 e g 6.35 54.61 h 1.27 (t.p.) i 8.89 j 24.495 k 42.18 l 17.78 m n r 4.00.1 q v 0.20.15 r2.0 4.0 max. 3.0 f p 1.0 y 3.0 min. w x 2.54 min. 1.00.05 z 3.0 min. w g v x y r s l q z j h c b k g i b de a (optional holes) a 38.1 detail of a part detail of b part
data sheet m13202ej3v0ds00 14 MC-458DA726 [memo]
data sheet m13202ej3v0ds00 15 MC-458DA726 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
MC-458DA726 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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